The present invention relates to a circuit that reduces external terminal or pin count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration data. More particularly, the invention relates to a circuit that reduces the number of external input terminals or pins required for generating the configuration data. The invention also relates to a method for generating configuration data for a semiconductor chip using a reduced number of external terminals or pins. The invention further relates to an Ethernet or network card in which the chip and circuit may be embodied and to which the configuration data generating method may be applied.
Communications integrated circuits (ICs), such as Ethernet chips, are becoming more common in computers as connections to local area networks (LANs), wide area networks (WANs), and other Intranet networks become more important in day-to-day business activities. As such chips become more widely used, they are also becoming more highly integrated to perform an increasing number of interface functions. The problem is that an increase in functionality tends to increase chip pin count.
In IC design it is desirable to provide more functions using the same number of pins, or to provide the same functions using fewer pins. Using fewer pins has the advantage of reducing the size of the chip and the expense of packaging the chip. For example, a design that uses only six pins to perform a certain function is superior to a design that requires eight pins to perform the same function.
One problem in conventional communications chip design is that certain input pins are used only to configure the chip during initialization of the chip, such as at start up. Once the chip is configured these input pins are not used for any other purpose. Thus, they simply increase chip size without providing any additional functionality.
Therefore, it would be desirable to provide a communications chip which minimizes the number of input pins required for configuration and which therefore reduces the overall pin count and size of the chip.
It is therefore an object of this invention to provide a communications chip having a reduced external terminal or pin count and therefore a reduced size.
According to one aspect of the invention, an integrated circuit is provided. The circuit comprises a plurality of multiplexers, each of which has a first input in communication with output data and a second input in communication with configuration data; a plurality of external output terminals in communication with an output of a respective one of the plurality of multiplexers; an external input terminal; and a memory in communication with the external input terminal. In operation, the external input terminal is connectable with a selected one of the plurality of external output terminals.
Preferably, the integrated circuit further comprises a signal generator in communication with the second input of each of the plurality of multiplexers.
Preferably, the configuration data comprises an n-bit sequence, and the memory comprises an n-bit shift register.
According to another aspect of the invention, the integrated circuit further comprises a second external input terminal and a second memory in communication with the second external input terminal, wherein the second external input terminal is connectable with a selected one of the plurality of external output terminals. In this case, the configuration data may comprise an n-bit sequence and an m-bit sequence, and the first memory comprises an n-bit shift register and the second memory comprises an m-bit shift register.
According to a further aspect of the invention, the integrated circuit may be formed on a circuit board which further includes a connector in communication with the external input terminal and selected one of the plurality of external output terminals. The circuit board may further include a plurality of light emitting diodes, each in communication with a respective one of the plurality of external output terminals.
According to yet another aspect of the invention, a method for configuring an integrated circuit is provided. The method comprises (a) selecting output data or configuration data to generate a plurality of output streams; (b) outputting from the integrated circuit each of the plurality of output streams; (c) inputting to the integrated circuit one of the plurality of output streams; and (d) storing configuration data input in step (c) when configuration data is selected in step (a).
The configuration data preferably comprises an n-bit sequence, and the memory means comprises an n-bit shift register.
According to still another aspect of the invention, a network communications system is provided which includes a computer system that comprises the above-described integrated circuit and a connector in communication with the external input terminal and a selected one of the plurality of external output terminals. The system may further include a plurality of light emitting diodes, each in communication with a respective one of the plurality of external output terminals.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.